
Design Verification Engineer
- Vancouver, BC
- Permanent
- Temps-plein
- Will demonstrate strong analytical thinking and problem-solving skills with an excellent attention to detail.
- Will have good communication and writing skills.
- Will have good teamwork and interpersonal skills.
- Closely work with architects and designers to develop verification strategies and execution plans.
- Participate in the verification of complex IP blocks, take end to end ownership of key features for all projects.
- Work on test plans, test case development, testbench enhancement, regression, and coverage closure.
- Deploying industry-leading verification methodologies, such as UVM and Formal Verification.
- Developing testbenches and verification components such as UVCs, models, BFMs, and re-usable verification environments.
- Writing, modifying, and maintaining constraint-random and directed test cases and libraries in System Verilog/UVM.
- Analyzing functional, code, and test plan coverage.
- Implementing assertions, checkers, and monitors.
- Triaging and debugging regressions.
- Reproducing functional bugs found in silicon, in simulation and/or Formal Verification tools.
- Conducting and participating in code reviews.
- Extensive hardware verification experience.
- Must be proficient in Verilog, System Verilog, UVM, and working in Linux and Windows environments.
- Must have ASIC design knowledge and be able to debug Verilog RTL code using simulation tools.
- Must have excellent programming skills.
- Must have exposure to Makefile and other scripting languages like Perl, Python and Ruby
- Bachelors or Masters degree in Computer Engineering/ Electrical Engineering