
ASIC Design Engineer
- Ottawa, ON
- Permanent
- Temps-plein
- Develop and implement RTL code and manage timing closures.
- Conduct detailed debugging to ensure high-quality design outputs.
- Engage in FPGA design and Verilog design, focusing on Telecoms and Data Center applications.
- Utilize TCL, PERL, and Python for coding tasks.
- Work on various design tools and protocols, including DFT, AXI, UCIE, and PCS.
- 5-10+ years of experience in ASIC/FPGA design.
- Proficiency in Verilog and RTL design.
- Experience with timing closures and kit tools.
- Familiarity with scripting languages such as TCL, PERL, and Python.
- Experience with OTN or Ethernet is highly desirable.
- Knowledge of additional protocols is beneficial.